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Seadog
Occasional Contributor
Occasional ContributorDDR3 timing errors on Cyclone V
Closing timing on a design using the 5CGTFD9E5F35C7, getting a few (17) setup failures on a DDR3 controller core; launch and latch clock are different, but both are part of DDR3 core. From: and to: ...
SeadogOccasional Contributor
Occasional ContributorSorry for the delay, I was otherwise occupied.
I just made the changes to the project and did a new build. The existing timing errors vanished. There is a new error, associated with the pll_afi_clk (150 MHz), for a single pair of nodes; the slack is -2 ps.
Thank you for your help with this problem.
