Forum Discussion
Occasional ContributorDDR3 timing errors on Cyclone V
Regular ContributorHi,
Yes I can see the timing issue there.
But when I setting the EMIF IP by following your EMIF configuration, the example design doesn't show any issue.
So do you able to provide any simple design or the example design that can replicate this issue?
Regards,
Adzim
Occasional ContributorI did a test build which contains just the EMIF core, a PLL and a reset circuit. I did not rebuild the EMIF core, I just made a copy of the existing item.
Unfortunately, the timing errors do not appear in this version of the design. In fact, the particular combinations of From Node, To Node, Launch Clock and Latch Clock which had errors in the original design do not even appear in the timing report for the test build (maybe this is a clue?).
I uploaded an archive of the test build, and a copy of the exported timing report form the original design.
