Forum Discussion
Seadog
Occasional Contributor
Occasional ContributorDDR3 timing errors on Cyclone V
Closing timing on a design using the 5CGTFD9E5F35C7, getting a few (17) setup failures on a DDR3 controller core; launch and latch clock are different, but both are part of DDR3 core. From: and to: ...
AdzimZM_Altera
Regular Contributor
Regular ContributorHi Seadog,
I already create an example design with your EMIF IP configuration.
The result is good.
No timing violation is occur.
Like I said in my previous feedback, this timing issue is not in the EMIF IP, it is occurring outside and at the custom logic.
Thus you can try some suggestions below:
- You can try to run a few seed sweep.
- Based on the recommendation from the Quartus, are you able to follow?
- Explore some compiler setting, choose mode with timing performance and compile.
Below is reference for duplicate register.
Regards,
Adzim
SeadogPlease excuse my obstinacy, but I am going back to what I wrote when I first posted this problem. All of the errors are associated with launch and latch clock edges which are coincident - the timing relationship is 0 ns. There is no available budget for asynchronous delays.
I have uploaded another document explaining the problem as I see it. Please explain to me why I am wrong.
