Forum Discussion
Seadog
Occasional Contributor
Occasional ContributorDDR3 timing errors on Cyclone V
Closing timing on a design using the 5CGTFD9E5F35C7, getting a few (17) setup failures on a DDR3 controller core; launch and latch clock are different, but both are part of DDR3 core. From: and to: ...
AdzimZM_Altera
Regular Contributor
Regular ContributorHi Seadog,
In that case, maybe you can share the timing report for Report DDR.
So that at least I can see where the timing issue occur.
Thanks,
Adzim
SeadogOccasional Contributor
Occasional ContributorI think the relevant information is in the spreadsheet I uploaded yesterday, but I am uploading the DDR timing report as a zip.
Thanks.
