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Seadog's avatar
Seadog
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

DDR3 timing errors on Cyclone V

Closing timing on a design using the 5CGTFD9E5F35C7, getting a few (17) setup failures on a DDR3 controller core; launch and latch clock are different, but both are part of DDR3 core. From: and to: ...
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi Seadog,


Thanks for using Intel Community.

I'm Adzim, AE that will assist you in this thread.


I really appreciate if you can share the design with me for replication purpose.


Thanks,

Adzim


  • Seadog's avatar
    Seadog
    Icon for Occasional Contributor rankOccasional Contributor
    4 years ago

    Hi Adzim,

    I can not share the design, it is ITAR restricted. I have attached a spreadsheet with the details on the errors. I can summarize the problem as well:

    • the 'From Nodes' and and 'To Node' (all errors are associated with the same 'To Node'), and the Launch and Latch Clocks are all internal to the DDR3 core
    • the Launch and Latch clock edges in question are coincident, thus the timing relationship (delay/skew budget) is 0.0 ns
    • there are numerous other paths using the same launch and latch clocks which do not have timing errors; the difference is that in the error cases, the latch clock is using the falling edge, whereas in the non-error cases, the latch clock uses the rising edge