Honored Contributor
Honored ContributorHi,
i have kind of the same problem. Maybe you could help me too? I work with the DBC5CEFA7 development board which include a Cyclone V FPGA and an already ready-to-go Nios II cpu. This cpu is embedded in a Quartus project and everything works fine. When i try to complie the unmodified i get the following error message. I dont really know what Qsys is missing here. The system is using two preset files for the DDR3 chips. The temp var is set to a local problem so thats not the case like in http://www.altera.com/support/kdb/solutions/rd02192013_986.html (http://www.altera.com/support/kdb/solutions/rd02192013_986.html) I also post a screenshot of my nios system.Error: s0: Error during execution of "{C:/program files/quartus/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormally
Error: s0: Execution of command "{C:/program files/quartus/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt" failed
Error: s0: ]2;Altera Nios II EDS 13.0 C:/program files/quartus/quartus/bin/uniphy_mcc -ac_code sequencer_mc/ac_rom.s -inst_code sequencer_mc/inst_rom.s -ac_rom ../nios_cpu_mem_if_ddr3_emif_h_s0_AC_ROM.hex -inst_rom ../nios_cpu_mem_if_ddr3_emif_h_s0_inst_ROM.hex -header sequencer/sequencer_auto.h -vheader ../sequencer_auto_h.sv -ac_rom_init sequencer/sequencer_auto_ac_init.c -inst_rom_init sequencer/sequencer_auto_inst_init.c -DAC_ROM_MR0=0001000100001 -DAC_ROM_MR0_CALIB= -DAC_ROM_MR0_DLL_RESET=0001100100000 -DAC_ROM_MR1=0000000000000 -DAC_ROM_MR1_OCD_ENABLE= -DAC_ROM_MR2=0000000000000 -DAC_ROM_MR3=0000000000000 -DAC_ROM_MR0_MIRR=0001001000001 -DAC_ROM_MR0_DLL_RESET_MIRR=0001011000000 -DAC_ROM_MR1_MIRR=0000000000000 -DAC_ROM_MR2_MIRR=0000000000000 -DAC_ROM_MR3_MIRR=0000000000000 -DQUARTER_RATE=0 -DHALF_RATE=0 -DFULL_RATE=1 -DGUARANTEED_READ_BRINGUP_TEST=0 -DMEM_ADDR_WIDTH=13 -DHARD_PHY=1
Error: s0: UniPHY Sequencer Microcode Compiler
Error: s0: Copyright (C) 1991-2010 Altera Corporation
Error: s0: Info: Reading sequencer_mc/ac_rom.s ...
Error: s0: Info: Reading sequencer_mc/inst_rom.s ...
Error: s0: Info: Writing ../nios_cpu_mem_if_ddr3_emif_h_s0_AC_ROM.hex ...
Error: s0: Info: Writing ../nios_cpu_mem_if_ddr3_emif_h_s0_inst_ROM.hex ...
Error: s0: Info: Writing sequencer/sequencer_auto_ac_init.c ...
Error: s0: Info: Writing sequencer/sequencer_auto_inst_init.c ...
Error: s0: Info: Writing sequencer/sequencer_auto.h ...
Error: s0: Info: Writing sequencer/sequencer_auto.h ...
Error: s0: Info: Writing ../sequencer_auto_h.sv ...
Error: s0: Info: Microcode compilation successful
Error: s0: C:/program files/quartus/quartus/../nios2eds/sdk2/bin/nios2-bsp hal sequencer_bsp .. --default_sections_mapping sequencer_mem --use_bootloader DONT_CHANGE
Error: s0: child process exited abnormally
Error: s0: Cannot find sequencer/sequencer.elf
Error: s0: An error occurred
while executing
"error "An error occurred""
(procedure "_error" line 8)
invoked from within
"_error "Cannot find $seq_file""
("if" then script line 2)
invoked from within
"if { == 0} {
_error "Cannot find $seq_file"
}"
(procedure "alt_mem_if::util::seq_mem_size::get_max_memory_usage" line 14)
invoked from within
"alt_mem_if::util::seq_mem_size::get_max_memory_usage ]"
("if" then script line 2)
invoked from within
"if { !$do_only_rw_mgr_mc && !($bfm_mode || $hps_mode)} {
set calc_mem_size > 0} {
set seq_mem_size "
(procedure "alt_mem_if::gen::uniphy_gen::generate_sequencer_files" line 3)
invoked from within
"alt_mem_if::gen::uniphy_gen::generate_sequencer_files $name "DDR3" $tmpdir QUARTUS_SYNTH"
invoked from within
"foreach generated_file {
set file_name [file tail $genera..."
(procedure "generate_synth" line 8)
invoked from within
"generate_synth nios_cpu_mem_if_ddr3_emif_h_s0"
Info: s0: "mem_if_ddr3_emif_h" instantiated altera_mem_if_ddr3_qseq "s0"
Error: Generation stopped, 37 or more modules remaining
Info: nios_cpu: Done nios_cpu" with 67 modules, 414 files, 9592561 bytes
Error: ip-generate failed with exit code 1: 20 Errors, 6 Warnings
Info: Finished: Create HDL design files for synthesis
