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I assume you are talking about the TCL files created when a QSYS design generates files. These files should not be added to your project in any way. They are not part of the project, but when run they add settings needed for proper operation of the memory controller.
When you generate files from QSYS, a message is shown telling you what script you need to run. Back in Quartus, you need to use the "Tcl scripts..." command in the tools menu to run the script the QSYS message told you to run.
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I'm actually talking about the SDC file that you mentioned-- If it is in the QIP file, then it should be read by Quartus. Otherwise it might need to be added manually in the SDC file list. Otherwise-- I'm not sure as I'm currently working on a board with no FPGA-based DDR, and can't remember the process. I'm sure someone else can chime in on that.
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