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Altera_Forum's avatar
Altera_Forum
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11 years ago

DDR3 Local_init_done not asserting

My company has our own proprietary design with two Micron MT41J64M16LA-15E DDR3 chips. For years we only used one chip as Quartus 10.0 had pin layout problems. Recently I have been trying to get the second bank up, which I finally got going. However the second memory controller fails to init once the board warms up. Obvously, timing. Can anyone give me a quick rundown of the init process handshaking with the DDR3? This is a Arria II GX part (EP2AGX45DF29I3).

After initialization, the part runs fine, and I can usually get the part to init with a little cold spray.

Thanks

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Have you tried running the External Memory Interface (EMIF) toolkit?

    When you build a UniPHY DDR controller via Qsys or the MegaWizard, and then look at the synthesized hierarchy you will see a JTAG master called dmaster (debug master). Use Tools->System Console->External Memory Interface Toolkit (Quartus 13.1) to access this tool.

    Run the margin tests, use quick-freeze if necessary to get it to pass.

    Perhaps that will provide some insight into the issue.

    Look at the PCB layout and see if the address/command signals are routed as a tree or as a fly-by like a DDR DIMM. Given that you are having problems with only the second bank, my "guess" is that you have a tree layout and have configured the controller to expect a fly-by layout (I believe I've seen a setting for this option).

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    EMIF does not work for Arria IIGX. I will look at the PCB layout and try to determine if its fly-by or tree. Thanks for the reply I really appreciate your help.