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Altera_Forum
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7 years ago

DDR3 hard memory controller usage issue

Hello all I have implemented a hard memory controller on the Altera Cylcone V SOC development board. The board calibrates successfully but when I write some thing to address '0' and try to read it...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

Just tried my VHDL interface code on a different development board which features the Cyclone V E, but the hard memory controller is not hooked up on that board.

So using the same code but this time on the soft memory controller and everything works fine. So I do not believe I am doing anything wrong as far as interfacing with the controller.

The question then becomes why does the hard memory controller not respond the same way as the soft controller?