Honored Contributor
Honored ContributorI believe I have set all the parameters correctly per the data sheet.
There is a discrepancy though between the Development board reference manual and the memory data sheet. The reference manual states CL = 9, however for this chip running at 400 Mhz (2.5ns period) the memory data sheet states that CL = 6 and CWL = 5. I have tried it both ways with the same results. The emif toolkit is not available for the Cyclone V SOC according to the External Memory Handbook. Is this not the case? IF the EMIF toolkit would work that would be great. Does anyone know the correct settings for the Altera Cyclone V SOC development board? Here are the settings that I am using which I pulled from the memory data sheet. Memory part number Micron D9PXV CL= 6 CWL = 5 tIS = 170 ps tIH = 120 ps tDS = 10 ps tDH = 45 ps tDQSQ = 100 ps tQH = 0.38 cycles tDQSCK 225 ps tDQSS = 0.27 cycles tQSH = 0.4 cycles tDSH = 0.18 cycles tINIT = 500 us tMRD = 4 cycles tRAS 35 ns tRCD = 15 ns tRP = 15 ns tREFI = 7.8 us tRFC 350 ns tWR 15 ns tWTR = 4 cycles tFAW = 40 ns tRRD = 10 ns tRTP = 10 ns Thanks!
