Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

DDR3 hard memory controller usage issue

Hello all I have implemented a hard memory controller on the Altera Cylcone V SOC development board. The board calibrates successfully but when I write some thing to address '0' and try to read it...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

If the timing parameters are correct you can debug with the protocol checker.

(Enable the EMIF toolkit debugging option and the efficiency monitor in the diagnostics tab of DDR3 controller settings)

There is also an example design in QSYS available.