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Altera_Forum
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7 years ago

DDR3 hard memory controller usage issue

Hello all I have implemented a hard memory controller on the Altera Cylcone V SOC development board. The board calibrates successfully but when I write some thing to address '0' and try to read it...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

Have you configured the Hard IP settings to correspond to that of the memory IC on the board from where you're writing and reading to? Have you set the CAS latency, RAS/CAS delay, etc? If the timing parameters are incorrect this can happen.