DDR3 DQ and DQS pin grouping

I'm trying to use the DDR3 SDRAM High Performance Controller on a Stratix IV GX device. I want to interface the FPGA to a 1GB registered DIMM. I can generate a controller, execute the pin_assignment tcl script, and synthesize my design, but I'm confused about the grouping of the DQ and DQS/DQSn signals.

The generated grouping assignments in my qsf file group the DQ and DQS signal incrementally (DQ[3:0] with DQS0, DQ[7:4] with DQS1, and so on); however, the RDIMM is expecting a different grouping of DQ and DQS signals (DQ[3:0] with DQS0, DQ[7:4] with DQS9, DQ[11:8] with DQS1, and so on). These two methods of grouping are incompatible, of course.

Even the DR3 SDRAM user guide is a little confusing. Page 47/178 of the user guide briefly outlines the two mapping methods (the same as I mentioned above), but doesn't indicate how to control which of the two methods occurs.

Has anyone dealt with this issue before?

How do I switch from one method to another? I can see in the qsf file where these assignments occur, but I don't necessarily want to change auto-generated code if I don't have to (and there's always the issue of incorrectly making changes).

Any input would be greatly appreciated.

Thanks,

Doug