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Altera_Forum
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13 years ago

DDR2 Timing Problem in Nios System on Stratix III dev.board

Hey ... I am a student and relatively new to the FPGA topic. I have an Altera DSP development board wit a Stratix III FPGA. I'm trying since a while to create a Nios II System which uses the D...
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Altera_Forum
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13 years ago

Hmm.. Timing Analysis results are good but the DDR2 Memory is still not working in the NIOS 2 Eclipse environment.

At the moment I dont know what can be the reason. This morning I tried the same system with the discrete Memory chips on the board and it worked quiet fine.

Do you can think of a possible reason?