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Altera_Forum
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13 years ago

DDR2 Timing Problem in Nios System on Stratix III dev.board

Hey ... I am a student and relatively new to the FPGA topic. I have an Altera DSP development board wit a Stratix III FPGA. I'm trying since a while to create a Nios II System which uses the D...
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Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Thanks for the hint.

I am compiling right now and then i will try it on the board and will let you know it resolved the problem.