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Altera_Forum
Honored Contributor
Honored ContributorDDR2 Timing Problem in Nios System on Stratix III dev.board
Hey ... I am a student and relatively new to the FPGA topic. I have an Altera DSP development board wit a Stratix III FPGA. I'm trying since a while to create a Nios II System which uses the D...
Altera_ForumHonored Contributor
Honored ContributorYup if your lauch and latch clock are different specially different in frequency then you are bound to violate timings.
You can set clock groups between the clocks like exapmle set_clock_groups -exclusive -group [get_clocks virtual_clk] -group [clk_in] -group [copy and paste the name of the pll generated clock exactly as reported with the hierarchy] i dont think the clock groups for virtual clock is required as it doesnt feeds any port but i am not 100 % sure so just keep it to be on the safer side.
