Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorDDR2 SDRAM on Stratix III (DE3)
Hello,
i have a DE3 board in which i want to includ the SDRAM. I created a Nios-uController and the DDR2 controller in the Megawizaard-plugin-manager. But how do i connect the IP-core with the Nios-cpu so i can use it? Is there a tutorial how to do this? thanks i n advance5 Replies
Altera_Forum.global_reset_n_to_the_altmemddr(system_reset_n),
.local_init_done_from_the_altmemddr(), .local_refresh_ack_from_the_altmemddr(), .local_wdata_req_from_the_altmemddr(), .mem_addr_from_the_altmemddr(mem_addr), .mem_ba_from_the_altmemddr(mem_ba), .mem_cas_n_from_the_altmemddr(mem_cas_n), .mem_cke_from_the_altmemddr(mem_cke), .mem_clk_n_to_and_from_the_altmemddr(mem_clk_n), .mem_clk_to_and_from_the_altmemddr(mem_clk), .mem_cs_n_from_the_altmemddr(mem_cs_n), .mem_dm_from_the_altmemddr(mem_dm), .mem_dq_to_and_from_the_altmemddr(mem_dq), .mem_dqs_to_and_from_the_altmemddr(mem_dqs), .mem_dqsn_to_and_from_the_altmemddr(mem_dqsn), .mem_odt_from_the_altmemddr(mem_odt), .mem_ras_n_from_the_altmemddr(mem_ras_n), .mem_we_n_from_the_altmemddr(mem_we_n), .oct_ctl_rs_value_to_the_altmemddr(), .oct_ctl_rt_value_to_the_altmemddr(), .reset_phy_clk_n_from_the_altmemddr(), see this post: http://www.alteraforum.com/forum/showthread.php?t=23412- Altera_Forum
I have the same problem witk DDR2 1GB added with board DE3.
Do someone know how to set memory. - Altera_Forum
The CD contains a DDR2 example in the DE3_demonstrations folder. Here are the connections to/from the NIOS given in verilog:
.clk(OSC1_50), .reset_n(system_reset_n), .in_port_to_the_pio_button(Button), .out_port_from_the_pio_led({LEDR, LEDG, LEDB}), .global_reset_n_to_the_altmemddr(system_reset_n), .local_init_done_from_the_altmemddr(), .local_refresh_ack_from_the_altmemddr(), .local_wdata_req_from_the_altmemddr(), .mem_addr_from_the_altmemddr(mem_addr[12:0]), .mem_ba_from_the_altmemddr(mem_ba[1:0]), .mem_cas_n_from_the_altmemddr(mem_cas_n), .mem_cke_from_the_altmemddr(mem_cke[0]), .mem_clk_n_to_and_from_the_altmemddr(mem_clk_n), .mem_clk_to_and_from_the_altmemddr(mem_clk), .mem_cs_n_from_the_altmemddr(mem_cs_n[0]), .mem_dm_from_the_altmemddr(mem_dm), .mem_dq_to_and_from_the_altmemddr(mem_dq), .mem_dqs_to_and_from_the_altmemddr(mem_dqs), .mem_dqsn_to_and_from_the_altmemddr(mem_dqsn), .mem_odt_from_the_altmemddr(mem_odt[0]), .mem_ras_n_from_the_altmemddr(mem_ras_n), .mem_we_n_from_the_altmemddr(mem_we_n), .oct_ctl_rs_value_to_the_altmemddr(), .oct_ctl_rt_value_to_the_altmemddr(), .reset_phy_clk_n_from_the_altmemddr(), .out_port_from_the_ddr2_i2c_scl(mem_SCL), .bidir_port_to_and_from_the_ddr2_i2c_sda(mem_SDA) - Altera_Forum
Ok, i tried it in SOPC Builder now.
I insert a -CPU -Onchipmem -JtagUart -Memmorycontroller -IOs for buttons and leds I now can compile the SOPC. the DDR2 settigns i made like they are in the DDR2 example. But when i Insert the NIOS-System in a Blockdiagramm it hat different amounts of ports then the one in the example has. these are the Pins i get when i use the DE§-SsystemBuilder to generate the ddr2 Pins:
but my Nios-System looks like this: http://robotik.dyyyh.de/fpga/nios.JPG in the ddr2 settings i made these settings: (i took these setting from the example-projekt which doesnt run :/ http://robotik.dyyyh.de/fpga/ddr2.JPG i dont know which pins i have to connect now.. The ram is a 1GB DDR2 SODIMM 667 from Transcend 509454-2608(which was included in whith the de3 board, but no datatsheet) could someone please help me, or is there a beginner tutorial for ddr2 on Stratix DE3 ??Button Button Button Button CLK_OUT EXT_CLK JVC_CLK JVC_CS JVC_DATAIN JVC_DATAOUT LEDB LEDB LEDB LEDB LEDB LEDB LEDB LEDB LEDG LEDG LEDG LEDG LEDG LEDG LEDG LEDG LEDR LEDR LEDR LEDR LEDR LEDR LEDR LEDR OSC1_50 OSC2_50 OSC_BA OSC_BB OSC_BC OSC_BD OTG_A OTG_A OTG_A OTG_A OTG_A OTG_A OTG_A OTG_A OTG_A OTG_A OTG_A OTG_A OTG_A OTG_A OTG_A OTG_A OTG_A OTG_CS_n OTG_D OTG_D OTG_D OTG_D OTG_D OTG_D OTG_D OTG_D OTG_D OTG_D OTG_D OTG_D OTG_D OTG_D OTG_D OTG_D OTG_D OTG_D OTG_D OTG_D OTG_D OTG_D OTG_D OTG_D OTG_D OTG_D OTG_D OTG_D OTG_D OTG_D OTG_D OTG_D OTG_DC_DACK OTG_DC_DREQ OTG_DC_IRQ OTG_HC_DACK OTG_HC_DREQ OTG_HC_IRQ OTG_OE_n OTG_RESET_n OTG_WE_n mem_SA mem_SA mem_SCL mem_SDA mem_addr mem_addr mem_addr mem_addr mem_addr mem_addr mem_addr mem_addr mem_addr mem_addr mem_addr mem_addr mem_addr mem_addr mem_addr mem_addr mem_ba mem_ba mem_ba mem_cas_n mem_cke mem_cke mem_clk mem_clk mem_clk_n mem_clk_n mem_cs_n mem_cs_n mem_dm mem_dm mem_dm mem_dm mem_dm mem_dm mem_dm mem_dm mem_dq mem_dq mem_dq mem_dq mem_dq mem_dq mem_dq mem_dq mem_dq mem_dq mem_dq mem_dq mem_dq mem_dq mem_dq mem_dq mem_dq mem_dq mem_dq mem_dq mem_dq mem_dq mem_dq mem_dq mem_dq mem_dq mem_dq mem_dq mem_dq mem_dq mem_dq mem_dq mem_dq mem_dq mem_dq mem_dq mem_dq mem_dq mem_dq mem_dq mem_dq mem_dq mem_dq mem_dq mem_dq mem_dq mem_dq mem_dq mem_dq mem_dq mem_dq mem_dq mem_dq mem_dq mem_dq mem_dq mem_dq mem_dq mem_dq mem_dq mem_dq mem_dq mem_dq mem_dq mem_dqs mem_dqs mem_dqs mem_dqs mem_dqs mem_dqs mem_dqs mem_dqs mem_dqsn mem_dqsn mem_dqsn mem_dqsn mem_dqsn mem_dqsn mem_dqsn mem_dqsn mem_odt mem_odt mem_ras_n mem_we_n - Altera_Forum
I'd use the SOPC builder, where you can create both modules and then connect them to eachothers with Avalon bus.
