DDR2 SDRAM on Stratix III (DE3)

The CD contains a DDR2 example in the DE3_demonstrations folder. Here are the connections to/from the NIOS given in verilog:

.clk(OSC1_50),

.reset_n(system_reset_n),

.in_port_to_the_pio_button(Button),

.out_port_from_the_pio_led({LEDR, LEDG, LEDB}),

.global_reset_n_to_the_altmemddr(system_reset_n),

.local_init_done_from_the_altmemddr(),

.local_refresh_ack_from_the_altmemddr(),

.local_wdata_req_from_the_altmemddr(),

.mem_addr_from_the_altmemddr(mem_addr[12:0]),

.mem_ba_from_the_altmemddr(mem_ba[1:0]),

.mem_cas_n_from_the_altmemddr(mem_cas_n),

.mem_cke_from_the_altmemddr(mem_cke[0]),

.mem_clk_n_to_and_from_the_altmemddr(mem_clk_n),

.mem_clk_to_and_from_the_altmemddr(mem_clk),

.mem_cs_n_from_the_altmemddr(mem_cs_n[0]),

.mem_dm_from_the_altmemddr(mem_dm),

.mem_dq_to_and_from_the_altmemddr(mem_dq),

.mem_dqs_to_and_from_the_altmemddr(mem_dqs),

.mem_dqsn_to_and_from_the_altmemddr(mem_dqsn),

.mem_odt_from_the_altmemddr(mem_odt[0]),

.mem_ras_n_from_the_altmemddr(mem_ras_n),

.mem_we_n_from_the_altmemddr(mem_we_n),

.oct_ctl_rs_value_to_the_altmemddr(),

.oct_ctl_rt_value_to_the_altmemddr(),

.reset_phy_clk_n_from_the_altmemddr(),

.out_port_from_the_ddr2_i2c_scl(mem_SCL),

.bidir_port_to_and_from_the_ddr2_i2c_sda(mem_SDA)