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Altera_Forum
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13 years ago

DDR2 interface pin planning issue

Hello, I'm working on a design that is going to use a Cyclone IV FPGA (EPCE75) including migration support for the EPCE30 and EPCE40 devices (F780 package). A lot of IO's will have to operate a...
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Altera_Forum
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12 years ago

Hi PaulusNL,

in my new design I have the same error message and I don't know how to work around.

I already changed the Dqs pin, but I still get the same error. What kind of pin swapping did you do?

I appreciate any help!