DDR2 Design with Cyclon III

Hi

I am still developing the board. Now I am just before starting to layout the PCB.

I have done a lot of simulating for signal integrity. I simulated for 167MHz Clock speed.

All traces impedanz controlled to approx. 50Ohm

This is what i found out:

- If i keep the lines below 3cm in length I don't need any termination due to reflexions

- Need to control drive strength in FPGA to eliminate over/undershoot

- Need to run DDR2 in reduced drive strength

- clock termination 100Ohm diff.

Bottom line is:

Except for clock there is no additional termination on board, but we need to reduce drive strength.

Alex