Forum Discussion
Honored ContributorDDR2 cyclone III FPGA dev kit
Hello,
I would like buy the Cyclone III FPGA dev kit. I see that they are on the kit 5 case of DDR2 SDRAM. So I would like know if the code for read and write on the cases is include in the kit. And if someone has ever use this kit and the DDR2 SDRAM. Thinks,18 Replies
Altera_ForumNo there is any message between the "Reading SDC file: 'altmemddr_phy_timing.sdc'" line and the big error message on the top of your screenshot. I will go install an old version of quartus and retry the operation
Thinks- Altera_Forum
It seems that Quartus has trouble processing the timing constraints file for the DDR controller. I'm not sure what's wrong exactly, but you should definitely try with 7.2 and see if you have the same problem.
Do you have any messages between the "Reading SDC file: 'altmemddr_phy_timing.sdc'" line and the big error message on the top of your screenshot? - Altera_Forum
I will go try to install quartus II 7.2
https://www.alteraforum.com/forum/attachment.php?attachmentid=507 - Altera_Forum
I still use Quartus II 7.2 SP3. Could you copy/past or upload the processing information you have in quartus' log before the "can't fit" error message?
- Altera_Forum
No I have just open the project and compile the file! Nothing else.
I use quartusII v8.0 - Altera_Forum
No I didn't have this problem. You should look at the messages before the "Can't fit design in device" to find where the problem comes from.
Did you make any change to the example design before compiling it? - Altera_Forum
Ok thinks, but when I want compile this exemple (nios 2 exemple) I have 4 errors.
Had you the same problem then you had comile the project? https://www.alteraforum.com/forum/attachment.php?attachmentid=506 But I have look the SOPC Builder of the exemple and I have see that only one case is use for the exemple. - Altera_Forum
Yes, the standard nios II example given with the development board includes the ddr2 controller megafunction, correctly configured and connected for the kit. It is only connected to 2 of the 5 chips though ("DDR2 bottom")
