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Altera_Forum's avatar
Altera_Forum
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17 years ago

DDR2 cyclone III FPGA dev kit

Hello, I would like buy the Cyclone III FPGA dev kit. I see that they are on the kit 5 case of DDR2 SDRAM. So I would like know if the code for read and write on the cases is include in the ki...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

It seems that Quartus has trouble processing the timing constraints file for the DDR controller. I'm not sure what's wrong exactly, but you should definitely try with 7.2 and see if you have the same problem.

Do you have any messages between the "Reading SDC file: 'altmemddr_phy_timing.sdc'" line and the big error message on the top of your screenshot?