DDR2 and DDR3 SDRAM High-Performance Controller

Hello std logic,

Sorry confusing you. In fact, I should make it clear. Actually, I am beginner of using ddr2 IP & nios II. I plan to use nios II to write/read data from ddr 2 controller. To use the toolkit, I need to instantiate the JTAG Avalon port & debug port into the example top level auto generated file as described in this document (http://www.altera.com/literature/hb/external-memory/emi_debug_hw.pdf?gsa_pos=1&wt.oss_r=1&wt.oss=debug%20tool%20kit%20ddr2 (http://www.altera.com/literature/hb/external-memory/emi_debug_hw.pdf?gsa_pos=1&wt.oss_r=1&wt.oss=debug%20tool%20kit%20ddr2)) pages 4-4 to 4-5. The document does not tell how to write/read data from ddr 2 controller. Is it possible to do it? If yes, can you provide me the guide on how to do it?

Where should I instantiate the JTAG Avalon port & debug port after adding nios II into the project? Is it the instatiantion file (.vhd) generated by SOPC builder?

Thanks.

Best Regards,

Dave.