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Altera_Forum's avatar
Altera_Forum
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13 years ago

DDR SDRAM interface for EP3C10E144

Hi Folks,

I am trying to work which pins I need to connect for DDR SDRAM on the 144pin version of the EP3C10 device.

I am a little confused:

I want to use a x16 memory device and so will need two DQS pins (DQS[1..0]), that much I understand (i think!). but I will also need 2 DM bits (LDM & UDM) but it appears on the pin out chart for the FPGA that there is only one DM bit.

Can I use regular IO to perform this task? Or is the FPGA I want to use only capable of supporting x8 memory devices? And therefore only uses one DM pin.

There also seems to be confusing information in the pinout table for this device against Chap 8 of the External Memory Interface for CYCLONE III. In this chapter the table8.1 suggest that DQS pins pins are only available on top & bottom, yet the pinout suggests that is available on top/bottom/left/right for the 144pin version. This is also compounded as later on in chapter 8, fig 8.3 suggest that there are indeed DQS pins for top/bottom/left/right.

I am SO confused.

all advice would be most welcome

D

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Hello Again Socrates :-)

    just to see what is required I generated the SDRAM controller in my CPU, and it still requires the use of DM bits (4 for a 32bit bus width). But now DQS is not required (obviously as it is no longer DDR).

    Did you mean SRAM and if so is there an SRAM controller core?

    Thanks for your help (once again!).

    D
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    No, I mean SDRAM. For SDRAM it doesn't matter which pin is connected to particular I/O, since SDRAM doesn't use DDR primitives and is not such timing critical.