Forum Discussion
Altera_Forum
Honored Contributor
13 years agoHello Again Socrates :-)
just to see what is required I generated the SDRAM controller in my CPU, and it still requires the use of DM bits (4 for a 32bit bus width). But now DQS is not required (obviously as it is no longer DDR). Did you mean SRAM and if so is there an SRAM controller core? Thanks for your help (once again!). D