Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

DDR Reflection Phenomenon

Hi everybody,

These days I have been asking some questions in relationship with some problems in a new pcb design and the communication between the Cyclone III and the DDR. Finally I think I have isolated the problem. I have made a test, sending pulses of 20 ns, periodically. In the first case 1 pulse every 1 usec. The second case 2 pulses every 1 usec, 3 pulses and so on. Here are the pictures. I deduced from the picture that exist reflections in the line.

This effect is observed in lines with SSTL2 class I standard. I'm goint to change the impedance of the active parallel termination for a higher one (instead of 56 ohm, 75 ohm) Any other idea in order to fix this problem?

Any help would be grateful,

Many thanks.

ifdm

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    The signal doesn't look extremely bad. You should clarify trace length and exact termination scheme, signal type+direction (I guess DQ+write), used probe and probing location. Without an active or high frequency resistive probe, the waveforms won't mean much, I think. Clear quare waveforms rather than "pulses" and ns time resolution would be suggested, too.

    You can refer to the respective DDR RAM termination application notes from Altera about a reasonable waveform display.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Post schematics and PCB tracing if possible, so it would be easier to find the problem... Are all DQ to DQS lengths within' DDR routing specs?

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Yes, I use series resistors of (25 ohm) and a pull up to (vccio/2) resistor of 56 ohm. These lines belongs to the addresses signals from the FPGA to the ddr-sdram. I attach the schematic and the pcb. The PCB characteristics are: 16 mil layer thick, fr4, cupper 1.4mil, 8mil track thick, 2850 x 2820 mil .

    I use a high impedance oscilloscope probe with an input impedance of 1 Mohm shunted by 20 pF .
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Hello,

    I have analyzed the signals again and probably the reflection isn't the cause of the problem. In the images, what is seen are some signals that arrive a little bit late or a bit sooner, and that's because appear 4 pulses when it is expected 3 pulses. Maybe there is another kind of problem.

    Thanks.