DDR PIN placement error

Hi Josy,

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In Cyclone IV the DQS is not used to capture the DDR2 data. This is stated several times in the Cyclone IV data-sheet. Instead ALT-MemPHY uses a phase-shifted clock from the PLL (that generates all memory clocks) to capture the data.

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Thanks for clarifying that. I am using the Stratix IV devices, and incorrectly assumed the interface was the same on the Cyclone IV devices. I'd had to use the Stratix IV pin assignment tables to try to figure out the assignments for DDR and QDR on the Stratix IV GX Development kit.

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It looks to me that all (most) IO-pins are created equal (DDR-out an OE registers etc. in the IO-cell, DDR-in registers in the logic fabric) so how come the DQ/DQS/DQM-pins are more equal? That is the mystery I'd like to see revealed.

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An interesting mystery indeed. Write a DDR2 interface independently of the Altera IP?

Cheers,

Dave