DDR PIN placement error

Hi Dave,

--- Quote Start ---

DDR2/3 interfacing requires phase shifting the strobe clock to capture the data.

--- Quote End ---

In Cyclone IV the DQS is not used to capture the DDR2 data. This is stated several times in the Cyclone IV data-sheet. Instead ALT-MemPHY uses a phase-shifted clock from the PLL (that generates all memory clocks) to capture the data. It looks to me that all (most) IO-pins are created equal (DDR-out an OE registers etc. in the IO-cell, DDR-in registers in the logic fabric) so how come the DQ/DQS/DQM-pins are more equal? That is the mystery I'd like to see revealed.

Regards,

Josy