DDR Output Constraining - "too positive" slack

Hi,

I hope someone knows the solution to the problem that kept me really busy lately :(

I have to connect to an RGMII PHY that has the following parameters:

tCLK = 8 (ns)

TskewR (Data to Clock input Skew) (at the PHY) : min 1.0 max 2.6 (ns) (from the RGMII datasheet)

I am supposed to meet the PHY requirements without the use of PLLs.

The problem I have is that Quartus gets a "too positive" slack - of more than 1/2 of tCLK - and still reports this slack as correct. In practice this kill sme since data would be captured with the wrong edge. Is there a way to specify a maximum slack? Are my constraints incomplete?

Attached is a TimeQuest wave report.

I used the following constraints:

# ################ #

derive_pll_clocks # # derives the pll_out[0] that will be used as output clock

create_generated_clock -name mtx_clk_ddr -offset 0 -source {pll_out[0]} [get_ports {mtx_clk_pad_o}]

set outclk "pll_out[0]"

set outclk_ddr "mtx_clk_ddr"

set_false_path -rise_from $outclk -fall_to $outclk_ddr -setup

set_false_path -fall_from $outclk -rise_to $outclk_ddr -setup

set_false_path -rise_from $outclk -rise_to $outclk_ddr -hold

set_false_path -fall_from $outclk -fall_to $outclk_ddr -hold

set_output_delay -clock $outclk_ddr -max 2.6 [get_ports {mtxd_pad_o

[*] mtxen_pad_o}]

set_output_delay -clock $outclk_ddr -min -1.0 [get_ports {mtxd_pad_o

[*] mtxen_pad_o}]

set_output_delay -clock $outclk_ddr -clock_fall -max -add_delay 2.6 [get_ports {mtxd_pad_o

[*] mtxen_pad_o}]

set_output_delay -clock $outclk_ddr -clock_fall -min -add_delay -1.0 [get_ports {mtxd_pad_o

[*] mtxen_pad_o}]

Thanks!