DDR Output Constraining - "too positive" slack

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Did you consider adding 1 pipeline cycle and swapping the data for high and low clock edges?

I don't recall all the (r)GMII details, but IIRC you can insert an extra cycle on the transmitter pipeline. The idea is to transmit on the opposite edge of the clock. This way you wouldn't need to delay the clock, because data would naturally be delayed with respect to the clock.

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And inverting the output clock... data is edge sensitive in RGMII. yes, that was taken into account. Decision involved some other factors as well.

Thanks for the help!