DDIO bitclock location and clkctrl blocks

Hi

I'm using a Stratix III EP3SL340 C3 (Terasic DE3) and I had a question about DDIO and where to place the bitclock with respect to data.

And if I should route it via clkctrl blocks.

I have 12 bit data from an ADC (AFE5807) coming in at 80MSPS. I wanted to use DDIO to receive the data. I'll deserialize it later.

I've run the attached sdc file for various pin configurations.

If I place clkctrl blocks after my bitclock, my timing is worse and fails in some data pairs.

(Q1 : Why is this so? Isn't periphery clock supposed to be cooler for this?)

Without placing a clkctrl block in front of the bitclk.

If I put the bit clock in the middle of the input pins i.e. {datapair on pins [8..5], bitclk on pin 4, datapair on pins [3..0]}

I get slightly better slack overall.

If I place the bit clock on one end of the data pairs i.e. {datapair on pins [8..1], bitclk on pin 0}

I get varying slacks decreasing as we move away from bitclk.

Is there a rule of thumb I'm missing as to where to ideally place the bitclk? Also, how about frame clocks as well. Middle of the data pairs or on one side? I know PLL routing is ideal, but I live in the real world without PLLs on convenient input pins :-P

And how is clock routing better without a periphery clock control block?

Thanks

ZubairLK