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Altera_Forum's avatar
Altera_Forum
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15 years ago

DCLK and DATA0 connected to LVDS output instead of floating

The Cyclone II handbook says that after programming, the DCLK and DATA0 inputs should not be left floating and should therefore be connected to a logic high or low. However, it also states that th...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

It would definitely be useful to perform a test before implementing it into device. Or perform a signal integrity simulation (e.g. in HyperLynx)