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Altera_Forum
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15 years ago

DCLK and DATA0 connected to LVDS output instead of floating

The Cyclone II handbook says that after programming, the DCLK and DATA0 inputs should not be left floating and should therefore be connected to a logic high or low. However, it also states that th...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Well, I'd still recommend keeping buffers, but if the price is of greater concern then at least make sure FPGA LVDS buffers can drive 100 m UTP cable.