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Altera_Forum
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15 years ago

DCLK and DATA0 connected to LVDS output instead of floating

The Cyclone II handbook says that after programming, the DCLK and DATA0 inputs should not be left floating and should therefore be connected to a logic high or low. However, it also states that th...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

After reconsidering my options, I conclude that I've almost come full circle. The best solution seems to be the extra flashrom on FPGAremote, and to ditch the Ti buffer chips, instead connect the (now) two LVDS pairs of the FPGA directly to the RJ-45, but add a Cooper Bussman 41206ESDA for surge protection (reactiontime <1ns), which is cheaper to boot (the buffer chips were more expensive).