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Altera_Forum
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16 years ago

DCLK and DATA0 connected to LVDS output instead of floating

The Cyclone II handbook says that after programming, the DCLK and DATA0 inputs should not be left floating and should therefore be connected to a logic high or low. However, it also states that th...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

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The thing with LVDS is that it's not a panacea for nCONFIG, it's better than LVTTL but it still will pickup poise on 100 m cable. The problem is that just a single spike on it will invalidate current remote FPGA configuration.

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Ok, I indeed had hoped that LVDS would be the panacea; but as I understand, even LVDS is susceptible to occasional misreads. Reconsidering, then the best alternative would seem to be the remote flashrom, and on the UTP cable, to reuse the former nCONFIG pair as an extra GND and PWR pair (although that makes me wonder if I then don't make myself vulnerable to unpaired currents through the powerlines).