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Altera_Forum
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15 years ago

DCLK and DATA0 connected to LVDS output instead of floating

The Cyclone II handbook says that after programming, the DCLK and DATA0 inputs should not be left floating and should therefore be connected to a logic high or low. However, it also states that th...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Well, as long as remote FPGA can handle unexpected behavior on the cable it's fine. Using a configuration flash for remote FPGA side is a valid idea.

The thing with LVDS is that it's not a panacea for nCONFIG, it's better than LVTTL but it still will pickup poise on 100 m cable. The problem is that just a single spike on it will invalidate current remote FPGA configuration.