DCLK and DATA0 connected to LVDS output instead of floating

The whole hardware design approach here is not going to work :)

First thing that you'll experience is sporadic remote FPGA reconfigurations due to noise pickup on 100 m nCONFIG line.

As to ESD then "human body model" is just one of the several ESD model. There is a "machine model" and most important for you - "cable discharge model" (http://www.national.com/an/an/an-1511.pdf). They differ greatly in the ESD power they can apply to you circuit (e.g 15kV "human" is not equivalent to 15 kV "cable").

You'd need a reliable way to configure remote FPGA. You might add a small flash-based micricontroller on the remote side with LVDS-to-LVTTL buffers, send FPGA configuration data to MCU over LVDS with some CRC. And then MCU configures FPGA.