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Altera_Forum's avatar
Altera_Forum
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15 years ago

DCLK and DATA0 connected to LVDS output instead of floating

The Cyclone II handbook says that after programming, the DCLK and DATA0 inputs should not be left floating and should therefore be connected to a logic high or low. However, it also states that th...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

One (curious) question: how many circuits are you going to build? Tens or thousands?

A construction on a roof is exposed to more 'lightning' than one thinks.

If you insert a 'live' RJ45 connector into its mating socket the sequence of making contact is undefined. Sometimes the Vcc makes and some signals make contact before the Gnd finally gets there. Some circuits do not survive this 'game of Russian roulette'.

The termination could be the Achilles' Heel. The slow slew on the TTL outputs may not be enough to get rid of reflections on the Dclk and Data0. If it turns out to be enough they represent a significant resistance of 50 ohm (or more). These resistances in combination with the mandatory 100 ohm termination to receive LVDS later will eat heavily into the signal swing of the TTL outputs. To quote Einstein: "Everything should be made as simple as possible, but not simpler."

Do you need 32 MHz signalling rate towards FPGAremote?