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Altera_Forum's avatar
Altera_Forum
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16 years ago

DCLK and DATA0 connected to LVDS output instead of floating

The Cyclone II handbook says that after programming, the DCLK and DATA0 inputs should not be left floating and should therefore be connected to a logic high or low. However, it also states that th...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

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Is a Cyclone II more likely to break due to spikes than some kind of dedicated LVDS driverchip?

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I think it is. A lot of LVDS interface chips have specified ESD strength in contrast to the FPGA.

I personally prefer isolation by ethernet transformers for external LVDS interfaces, but it's involving additional effort for a DC balanced physical layer.