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Honored Contributor
Honored ContributorDCLK and DATA0 connected to LVDS output instead of floating
The Cyclone II handbook says that after programming, the DCLK and DATA0 inputs should not be left floating and should therefore be connected to a logic high or low. However, it also states that th...
Altera_ForumHonored Contributor
Honored Contributor100 m over CAT5 is different ballgame than what I had visualised.
I personally wouldn't connect a cable directly to a FPGA. Any disturbance on the cable could kill off the FPGA(s). The direct connection to config_n may/will be vulnerable to disturbances as well. My suggestion is to do everything in LVDS using external drivers/receivers. To make up for the missing signals you could add a MAXII to (safely) decode the configuration from the 2nd incoming LVDS line.
