Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

DCFIFO - incorrect functionality of a ModelSim timing simulation

Hey guys, A brief background:My VHDL design (for Stratix III) has input data arriving at 20MHz. The data is read at a rate of 100Mhz. The reading and writing operations aren't necessarily simul...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Hey ramanadn,

Please follow these steps:

1. Define the relevant simulation settings (note the bottom ones in case you have a test bench) in: assignments -> settings -> eda -> simulation.

In the "More NativeLink Settings" definge the way you want the scripts to be generated.

2. Compile the design.

3. In the output directory you've defined in the simulation settings (stage 1) you'll find the scripts you are looking for (with a .do suffix).

4. You can run these scripts in the third party tool directly from Quartus by choosing Tools -> Run EDA simulation tool -> EDA gate level simulation.

Hope this helps. Ask further if not.

Yoni.