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Altera_Forum
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16 years ago

DCFIFO - incorrect functionality of a ModelSim timing simulation

Hey guys, A brief background:My VHDL design (for Stratix III) has input data arriving at 20MHz. The data is read at a rate of 100Mhz. The reading and writing operations aren't necessarily simul...
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Altera_Forum
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16 years ago

Hey Daixiwen,

Thanks again for your help and advice. I will examine the document more thoroughly as soon as I'll need to perform full design synthesis.

Yoni.