Honored Contributor
Honored Contributor1. This is my mistake... I removed the virtual clocks to check if it changed anything, but forgot to put them back in
2. The actual hold (delay between the clock edge and the time the signal is allowed to change) is the *opposite* of the output min delay. I don't know why they put it like this. But again the actual value depends on the external components' requirements, and the pcb delays. The document in this thread (http://www.alteraforum.com/forum/showthread.php?t=1269) explains it well, and give practical examples (which in my opinion the Altera documentation lacks). Opening the Timequest analyser and using the report timing function also helps to understand how your requirements are interpreted. I agree that my setting doesn't necessarily make the fitter job any easier, but neglecting the hold requirements can cause problems in "fast" conditions (high supply voltage and low temperature).
