DCFIFO - incorrect functionality of a ModelSim timing simulation

Hello Daixiwen,

I would like to thank you for your detailed reply and for the time you spent to compile & simulate my code.

In the meanwhile, I have applied a service request on Altera's mySupport. They have helped me to solve the problem. To cut a long story short, I've discovered that by modifying the Quartus settings, it can be tolled to generate a ModelSim script for an appropriate rtl / gate level simulation. Using such a script, I've been able to simulate my design and achieve correct functionality, thus putting an end to this miserable saga.

I have examined your last reply, though, and I still have some questions:

1. How come the .sdc file you've suggested does not contain any virtual clocks ? I thought those were necessary, quoting the QII version 10.0 HandBook, Volume 3, chapter 7:
   --- Quote Start ---
   For I/O interface uncertainty, you must create a virtual clock and constrain the input
   and output ports with the set_input_delay and set_output_delay commands
   that reference the virtual clock. The virtual clock is required to prevent the
   derive_clock_uncertainty command from applying clock uncertainties for
   either intra- or inter-clock transfers on an I/O interface clock transfer when the
   set_input_delay or set_output_delay commands reference a clock port or
   PLL output.
   --- Quote End ---

2. What is the meaning of a negative value for the minimum output delay ? When I examine the equation Altera proposes to derive this delay, I figure that a negative value suggests that the hold time for the output latch (external to the FPGA device) is longer than the minimal delay path leading to this latch. Thus, Quartus has to place the logic to create extra (in our case) 2.0 ns of contamination delay to make sure that the hold requirement is met. I find it hard to believe that this will make the compilation job for Quartus any easier (I also checked and so that it caused a smaller f_max). Am I missing something ?

Again, thank you for your kind help. The advice you gave me allowed for a great improvement in my digital design skills.

Yoni.