DCFIFO - incorrect functionality of a ModelSim timing simulation

I tried your project on my system (Quartus 9.0 SP2 and Modelsim 6.4a) and didn't have the same results.

First Quartus couldn't meet the timing requirements. I don't know what are your actual I/O timings, but I tweaked a bit the sdc file to make the job easier for Quartus. I didn't try to enable any optimizations or set fast paths/registers. I changed the .sdc file to this:

create_clock -period 10.000 -name read_clk 
create_clock -period 50.000 -name write_clk 
derive_clock_uncertainty
set_input_delay -clock { read_clk } -max 2.0 
set_input_delay -clock { read_clk } -min 0.0 
set_input_delay -clock { write_clk } -max 2.0 
set_input_delay -clock { write_clk } -min 0.0 
set_input_delay -clock { write_clk } -max 3.0 
set_input_delay -clock { write_clk } -min 1.0 
set_output_delay -clock { read_clk } -max 0.4 
set_output_delay -clock { read_clk } -min -2.0 
set_output_delay -clock { write_clk } -max 0.4 
set_output_delay -clock { write_clk } -min -2.0 

But of course you should set requirements that are compatible with what you connect to the FPGA.

Then to run the timing analysis in Modelsim I added some lines to your script:

vlib lib
vmap work lib
vcom -O0 project/simulation/modelsim/DCFIFO_inst_4l_900mv_100c_slow.vho
vcom -O0 VHDL/DCFIFO_inst_tb_rtl.vhd
vsim -novopt -L altera_mf -t ps +transport_int_delays +transport_path_delays -sdfmax /DCFIFO_inst_tb/eut_DCFIFO_inst=project/simulation/modelsim/DCFIFO_inst_4l_900mv_100c_vhd_slow.sdo DCFIFO_inst_tb
add wave  -color green   sim:/DCFIFO_inst_tb/rst
add wave  -color orange  sim:/DCFIFO_inst_tb/read_clk
add wave  -color orange  -unsigned sim:/DCFIFO_inst_tb/read_data
add wave  -color orange  sim:/DCFIFO_inst_tb/read_enable
add wave  -color orange  sim:/DCFIFO_inst_tb/FIFO_empty
add wave  -color magenta  sim:/DCFIFO_inst_tb/write_clk
add wave  -color magenta  -unsigned sim:/DCFIFO_inst_tb/write_data
add wave  -color magenta  sim:/DCFIFO_inst_tb/write_enable
add wave  -color magenta  sim:/DCFIFO_inst_tb/FIFO_full
add wave  -color yellow  sim:/DCFIFO_inst_tb/good_result
add wave  -color pink    sim:/DCFIFO_inst_tb/done
run -all
wave zoomfull

where 'project' is the path to the Quartus project.

When I ran the simulation I had timing violations at the beginning. Changing the test bench so that the clocks start at 0 instead of 1 fixed it. I'm not used to perform timing simulations so I don't know if this is normal or not. Nevertheless, the simulation ran fine. So I don't know if your problem comes from a different setting somewhere, or a bug in Quartus 10.0