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Honored Contributor
Honored ContributorDCFIFO - incorrect functionality of a ModelSim timing simulation
Hey guys, A brief background:My VHDL design (for Stratix III) has input data arriving at 20MHz. The data is read at a rate of 100Mhz. The reading and writing operations aren't necessarily simul...
Altera_ForumHonored Contributor
Honored ContributorOh, there are two things I forgot to mention:
- I have attempted synthesizing for Stratix IV and witnessed the same incorrect behavior.
- I am using a tcl script for the ModelSim simulation (see attached).
