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Honored Contributor
Honored ContributorDCFIFO - incorrect functionality of a ModelSim timing simulation
Hey guys, A brief background:My VHDL design (for Stratix III) has input data arriving at 20MHz. The data is read at a rate of 100Mhz. The reading and writing operations aren't necessarily simul...
Altera_ForumHonored Contributor
Honored ContributorHey Daixiwen,
--- Quote Start --- Timequest doesn't produce an error when they aren't met, just a critical warning. --- Quote End --- I have checked that no warnings regarding the timing requirements were produced during the Quartus compilation. At your request, I have written a code for the dcfifo instantiation and a simple test bench for it. The test bench demonstrates the problem I am facing. Additionally, I have added the constraints file and the vho+sdo files produced by Quartus. The waves for the logic and timing simulations (performed in ModelSim SE 6.5b) are also attached. The incorrect functionality of the post synthesis dcfifo will be clear when you compare those two waveforms. I am very grateful for your intention on helping me. Yoni.
