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Honored Contributor
Honored ContributorDCFIFO - incorrect functionality of a ModelSim timing simulation
Hey guys, A brief background:My VHDL design (for Stratix III) has input data arriving at 20MHz. The data is read at a rate of 100Mhz. The reading and writing operations aren't necessarily simul...
Altera_ForumHonored Contributor
Honored ContributorTimequest is difficult to learn but it is time well spent ;)
Are you sure that the timing requirements are met? Timequest doesn't produce an error when they aren't met, just a critical warning. Could you post your code (fifo instantiation, sdc file and testbench)?
