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Altera_Forum
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16 years ago

DCFIFO - incorrect functionality of a ModelSim timing simulation

Hey guys, A brief background:My VHDL design (for Stratix III) has input data arriving at 20MHz. The data is read at a rate of 100Mhz. The reading and writing operations aren't necessarily simul...
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Altera_Forum
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16 years ago

Thank you for the advice, Daixiwen.

I went through an agonizing process of getting familiar with the TimeQuest analyzer. Currently, I managed to get zero unconstrained paths and zero failed paths (no red colored lines in the timing report). I have also made sure that my test bench drives the inputs in agreement with the input delay constraints, as defined in the .sdc file.

Nevertheless, the timing simulation in ModelSim exhibits the exact same problem which I described earlier.

Any other thoughts of what might be the problem ?

Should I try changing the target FPGA device to uncover the bug ?

Thanks,

Yoni.