I am new to interface FPGAs with DSP concepts. I have ADCs and then i have deserializers after them to parallelize the data. So should i apply the DC removal after the deserializer or before it? Also, i need guidence regarding the DC removal.I have studied about it but got nothing as a final conclusion that whether to apply a HPF or LPF and then a subtractor. Please provide help required urjectly.

See my post at: http://www.alteraforum.com/forum/showthread.php?t=29991&highlight=dc+filtering&page=2 you filter your data when parallelised into readable samples.

--- Quote Start --- I am new to interface FPGAs with DSP concepts. I have ADCs and then i have deserializers after them to parallelize the data. So should i apply the DC removal after the deserializer or before it? --- Quote End --- Can you control the DC offset in the analog domain? If so, it would be better to eliminate it there, as then you can use the full dynamic range of your ADC. Where is this DC coming from? If your ADC is AC-coupled, then the DC could be due to a bad input offset voltage, which some ADCs provide controls to eliminate. If your ADC is DC coupled, then you need to decide why its DC coupled, and decide if you want to change to AC coupling for your current application. --- Quote Start --- Also, i need guidence regarding the DC removal.I have studied about it but got nothing as a final conclusion that whether to apply a HPF or LPF and then a subtractor. --- Quote End --- What is the signal you are trying to measure? If you are digitally demodulating your signal and then filtering it, its quite possible your digital filter will be sufficient to remove the DC. Whether this would be sufficient, depends on how much DC is getting into your system, i.e., if you have a huge DC spike, then your filter stop-band rejection might need to be very high to remove it. You can also use the methods Kaz suggests in the thread he references, or a combination of DC removal filter, followed by digital demodulation and further filtering. Cheers, Dave

I understand the method provided by Kaz, i think. But i lag the connection of how do we implement this DC filter using FPGAs, as this would would be my first attempt to try some DSP usinf FPGAs. I have data from a transducer and it is being passed through ADc and then deserialized. I will check for the DC and AC coupling. But if i am right, i need to simulate this model using matlab to atleast figure out the basics of how moving average filter works. Thankx

Also, why are IIR recommended, can we use FIR too? I would be thankful for any help in form of any manuals or tutorials for implementation of these concepts in equivalent verilog (FPGA) domain?

--- Quote Start --- why are IIR recommended, can we use FIR too? --- Quote End --- Either will work. Ultimately it comes down to filter performance versus FPGA resources; IIRs can be more efficient, but they can have issues with stability and phase non-linearity, however, these issues can be overcome. --- Quote Start --- I would be thankful for any help in form of any manuals or tutorials for implementation of these concepts in equivalent verilog (FPGA) domain? --- Quote End --- Here's a tutorial you can look at, with associated VHDL http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-100paper_hawkins.pdf (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/esc-100paper_hawkins.pdf) http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-100slides_hawkins.pdf (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/esc-100slides_hawkins.pdf) http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-100slides_hawkins.zip (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/esc-100slides_hawkins.zip) http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc2011_fpga_dsp_code.zip (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/esc2011_fpga_dsp_code.zip) Cheers, Dave

DC offset removal using FPGA? | Altera Community

23 Replies

Altera_Forum
Honored Contributor
14 years ago
Dear DWH： I must show my thanks for your kindly help！ Ｉthink I would have more questions. I'll come back if I don't deal with. Thanks again! Jerry
Altera_Forum
Honored Contributor
14 years ago
Hi DWH,

Maybe you can make me clear whether the AC couple of the differential ADC just eliminate the DC (or noise) of the signal source, but there also is intrinsic DC of the ADC devices?
Altera_Forum
Honored Contributor
14 years ago
--- Quote Start ---

Maybe you can make me clear whether the AC couple of the differential ADC just eliminate the DC (or noise) of the signal source, but there also is intrinsic DC of the ADC devices?
--- Quote End ---
AC coupling just breaks the DC path from the signal source to the ADC pins.

The DC value on the ADC pins is then determined by the ADC. Ideally the ADC manufacturer designed the part so that it defaults to a DC level that corresponds to the mid-range of the ADC output codes. However, there is no guarantee of that, so you have to check. For example, I have used ADCs with track-and-hold DC offset control, so that you can adjust the DC level of an AC coupled ADC.

Cheers,
Dave

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DC offset removal using FPGA?

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